This invention relates to power source circuits for supplying source power or voltage to semiconductor devices such as memory ICs (integrated circuits).
FIG. 6 is a circuit diagram showing the structure of a conventional power source circuit. A P-channel field effect transistor 1 is coupled across an input terminal 2 and an output terminal 3. Serially connected resistors 4 and 5 are coupled across the input terminal 2 and a grounded terminal 6. The inverted input terminal of a comparator 7 is coupled to the junction point between the resistors 4 and 5, the non-inverted input terminal thereof being coupled to a constant voltage source 10. The output terminal of a comparator 7 is coupled to the gate of the P-channel field effect transistor 1.
The method of operation of the circuit of FIG. 6 is as follows. When a positive voltage is applied on the input terminal 2, the voltage applied on the inverted input terminal of the comparator 7 becomes higher than the voltage applied on the non-inverted input terminal thereof, such that the output of the comparator 7 is reduced to the low level L. As a result, the P-channel field effect transistor 1 is turned on, and the voltage applied on the input terminal 2 is output to the output terminal 3.
The conventional power source circuit of FIG. 6, however, has the following disadvantage. If the voltage applied on the input terminal 2 rises sharply, the voltage at the output terminal 3 also rises sharply. As a result, the voltage supplied to the memory IC, etc, coupled to the output terminal 3 rises abruptly. Thus the requirement for the predetermined rising rate of the power supply for the memory IC cannot be met. The memory IC may thus malfunction. Further, in the case of the memory IC which needs a backup voltage, the data stored therein may be changed or lost.